As it may be known, for non-volatile memory (which may include a floating-gate MOS transistor) reading a cell implies steps of address decoding the memory cell to be read, steps of routing the voltages for biasing the row and column lines which identify the cell within the array, and a step of sensing the cell content, with buffering the read data, which may be made available on a memory output pin.
To read a word within the memory, an address is decoded which may identify, univocally, a well-defined location within the cell array. The time needed to decode the address remarkably affects the access time of the memory, and therefore it may be the subject of continuous attempts of optimization.
Upon the increase of the dimensions of single partitions of memory cells forming the memory matrix, the length of the conductive paths which carry the address signals becomes higher, and it may become the element restricting the access time reduction. In particular, in some flash memories, the column decoding is structured hierarchically. In such memories, the memory matrix is organized in sectors (made of cell arrays) to which local decoders are coupled, whereas a set of more sectors (partition) is associated with the same global decoder. The partition is the group of sectors which share the same bank of sense amplifiers.
In such memories, a global address generator drives the global address bus, which reaches the plurality of local decoders. Such an address bus may be schematized as an RC net, and it may also be millimeters in size, representing one of the causes of the increasing access time.
According to the prior art, attempts have been made to reduce the time to access the sector forming the memory matrix, properly size the bus (width of the single wire and relative spacing between a wire and those adjacent), and act upon the dimensions of the address generator which drives the bus.